The present invention is related to comparators, and more particularly to high speed latching comparators.
Various comparators have been developed that allow for comparing two analog input signals and providing a digital output signal indicating the result of the comparison. FIG. 1 shows one such latched comparator circuit 100 that includes both a pre-amplifier and a latch. In operation, a bias voltage 178 (VBB1) is applied to a transistor 136 that causes a tail current to traverse from a rail voltage VDD 172 to a ground VSS 180 via a bias resistor 110. Each of two voltage inputs are applied to respective ones of an input IN 174 and an input INZ 176. The voltage at the collector of transistor 132 is replicated (i.e., less a base to emitter voltage drop) at the emitter of a transistor 142 that is configured as an emitter follower. Similarly, the voltage at the collector of transistor 134 is replicated (i.e., less a base to emitter voltage drop) at the emitter of a transistor 144 that is configured as an emitter follower. Transistor 142 is biased by a transistor 138 and resistor 112, and transistor 144 is biased by a transistor 140 and resistor 114. The emitter of transistor 142 and the emitter of transistor 144 are coupled to respective inputs of a differential input pair 147. In particular, the emitter of transistor 142 is electrically coupled to the base of a transistor 148, and the emitter of transistor 144 is electrically coupled to the base of a transistor 146. Thus, the respective voltages at the collectors of transistor 132 and transistor 134 are replicated (less a base to emitter voltage drop) on the respective bases of transistor 146 and transistor 148.
Whenever a clock input 192 (CK) is asserted high with respect to clock input 194 (CKZ), current is steered through differential input pair 147 in a fashion dependent upon the relative assertion levels of IN 174 and INZ 176. In particular, differential input pair 147 is biased by a transistor 154, a resistor 116 and voltage VBB1; and a tail current generated by the bias is differentially steered through transistor 146 and transistor 148 in proportion to the relative assertion levels of IN 174 and INZ 176. This results in a differential voltage across the collectors of transistor 146 and transistor 148. This differential voltage is applied across the base of a transistor 160 and the base of a transistor 162. The emitter of transistor 160 is electrically coupled to a comparator output 187 (OUTB), and the emitter of transistor 162 is electrically coupled to a comparator output 189 (OUTA). Together OUTA 189 and OUTB 187 operate as a differential output. Transistor 160 is biased by a transistor 164, a resistor 118 and VBB1, and transistor 162 is biased by a transistor 166, a resistor 120 and VBB1.
OUTA 189 and OUTB 187 are fed back to a differential input pair 157. In particular, OUTA 189 is electrically coupled to the base of a transistor 156, and OUTB 187 is electrically coupled to the base of a transistor 158. When CKZ 194 is asserted high (i.e., when CK 192 is asserted low), the tail current produced by transistor 154 and resistor 116 is steered through differential input pair 157 via a transistor 152. This results in a positive feedback of OUTA 189 and OUTB 187 that causes the aforementioned outputs to be latched. Thus, when CK 192 is asserted high, latched comparator circuit 100 is transparent, and when CK 192 is asserted low latch comparator circuit 100 latches the data.
In operation, when IN 174 is much greater than INZ 176, the tail current set up by transistor 136 is steered through transistor 132 and a resistor 102. Thus, the collector of transistor 134 is driven to approximately the level of VDD 172, and the collector of transistor 132 is driven to a lower voltage level (i.e., VDD−Itail*R102). This voltage difference is replicated across the bases of transistor 146 and transistor 148 as set forth in the following equations:Vb,148=VDD−Itail*R102−Vbe, andVb,146=VDD−Vbe.When CK 192 is asserted high, the aforementioned voltages are reflected at OUTA 189 and OUTB 187 according to the following equations:OUTA189=VDD−Vbe, andOUTB187=VDD−Itail*R108−Vbe, assuming Itail is the same in all legs of the circuit.When CK 192 is asserted low, OUTA 189 and OUTB 187 are latched via a positive feedback loop including differential input pair 157.
In contrast, when IN 174 is much less than INZ 176 the tail current set up by transistor 136 is steered through transistor 134 and a resistor 104. Thus, the collector of transistor 132 is driven to approximately the level of VDD 172, and the collector of transistor 134 is driven to a lower voltage level (i.e., VDD−Itail*R104). This voltage difference is replicated across the bases of transistor 146 and transistor 148 as set forth in the following equations:Vb,148=VDD−Vbe, andVb,146=VDD−Itail*R104−Vbe.When CK 192 is asserted high, the aforementioned voltages are reflected at OUTA 189 and OUTB 187 according to the following equations:OUTA189=VDD−Itail*R106−Vbe, andOUTB187=VDD−Vbe, assuming Itail is the same in all legs of the circuit.When CK 192 is asserted low, OUTA 189 and OUTB 187 are latched via a positive feedback loop including differential input pair 157.
As will be appreciated, transistors 142, 144 provide a valuable pre-amplifier function, that while useful consumes considerable power during operation of the previously described latched comparator circuit. Such power consumption is undesirable. Hence, for at least the aforementioned reasons, there exists a need in the art for advanced systems and methods for implementing comparators.